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1/19 AN1518 application note june 2002 l5973d introduction the l5973d is a step down monolithic power switching regulator capable to deliver up to 2.5a at output voltages from 1.235v to 35v. the operating input voltage ranges from 4.4v to 36v. it is realized in bcdv technology and the power switching element is realised by a p-channel d-mos transistor. it doesnt require a bootstrap capac- itor, and the duty cycle can range up to 100%. an internal oscillator fixes the switching frequency at 250khz. this minimizes the lc output filter. synchronization pin is available in the case higher frequency (up to 500khz) is requested. pulse by pulse and frequency foldback overcurrent protections offer an effective short circuit protection. other features are voltage feed forward, protection against feedback disconnection, inhibit and thermal shut- down. the device is housed in an hsop8 package with exposed pad that helps to reduce the thermal resistance jiunction to ambient (r thj-a ) down to approximately 40c/w. figure 1. demoboard l5973d (hsop8) board dimensions: 23 x 20 mm figure 2. package figure 3. pins connection hsop8 - exposed pad out sync inh comp 1 3 2 4 vcc vref gnd fb 8 7 6 5 d98in955 by massimiliano merisio designing with l5973d, up to 2.5a high efficiency dc/dc converter
AN1518 application note 2/19 pins functions block diagram figure 4. block diagram n. name description 1 out regulator output. 2 sync master/slave synchronization. when it is open, a signal synchronous with the turn-off of the inter- nal power is present at the pin. when connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal. connecting together the sync pin of two devices, the one with the higher frequency works as master and the other one, works as slave. 3 inh a logical signal (active high) disables the device. with ihn higher than 2.2v the device is off and with inh lower than 0.8v, the device is on. if inh is not used the pin must be grounded. when it is open, an internal pull-up disables the device. 4 comp e/a output to be used for frequency compensation. 5 fb stepdown feedback input. connecting the output voltage directly to this pin results in an output voltage of 1.235v. an external resistor divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is 4.7k). 6v ref reference voltage of 3.3v. no filter capacitor is needed to stability. 7 gnd ground. 8v cc unregulated dc input voltage. inhibit voltages monitor peak to peak current limit thermal shutdown e/a pwm 1.235v + - - + oscillator d ck q frequency shifter trimming supply 1.235v 3.5v driver v ref buffer lpdmos power fb sync comp inh v ref gnd out vcc d00in1125
3/19 AN1518 application note functional description the main internal blocks are shown in fig. 4, where is reported the device block diagram. they are: n a voltage regulator that supplies the internal circuitry. from this regulator, a 3.3v reference voltage is externally available. n a voltage monitor circuit that checks the input and internal voltages. n a fully integrated sawtooth oscillator whose frequency is 250khz 15%, including also the voltage feed forward function and an input/output synchronization pin. n two embedded current limitations circuitries which control the current that flows through the power switch. the pulse by pulse current limit forces the power switch off cycle by cycle if the current reaches an internal threshold, while the frequency shifter reduces the switch- ing frequency in order to strongly reduce the duty cycle. n a transconductance error amplifier. n a pulse width modulator (pwm) comparator and the relative logic circuitry necessary to drive the internal power. n an high side driver for the internal p-mos switch. n an inhibit block for stand-by operation. n a circuit to realize the thermal protection function. power supply &voltage reference the internal regulator circuit (shown in figure 5) consists of a start-up circuit, an internal voltage preregulator, the bandgap voltage reference and the bias block that provides current to all the blocks. the starter gives the start-up currents to the whole device when the input voltage goes high and the device is enabled (inhibit pin connected to ground). the preregulator block supplies the bandgap cell with a preregulated voltage v reg that has a very low supply voltage noise sensitivity. voltages monitor an internal block senses continuously the v cc , v ref and v bg . if the voltages go higher than their thresholds, the regulator starts to work. there is also an hysteresis on the v cc (uvlo). figure 5. internal regulator circuit starter ic bias preregulator bandgap vreg vref d00in1126 v cc
AN1518 application note 4/19 oscillator & synchronizator figure 6 shows the block diagram of the oscillator circuit. the clock generator provides the switching frequency of the device that is internally fixed at 250khz. the frequency shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. the clock signal is then used in the internal logic circuitry and is the input of the ramp generator and synchronizator blocks. the ramp generator circuit provides the sawtooth signal, used to realize the pwm control and the internal volt- age feed forward, while the synchronizator circuit generates the synchronization signal. infact the device has a synchronization pin that can works both as master and slave. as master to synchronize external devices to the internal switching frequency. as slave to synchronize itself by external signal up to 500khz. in particular, connecting together two devices, the one with the lower switching frequency works as slave and the other one works as master. to synchronize the device, the sync pin has to pass from a low level to a level higher than the synchronization threshold with a duty cycle that can vary approximately from 10% to 90%, depending also on the signal frequen- cy and amplitude. the input can be driven directly from a ttl logic signal and the synchronization signal must be at least higher than the internal switching frequency of the device (250khz). figure 6. oscillator circuit block diagram current protection the l5973d has two current limit protections, pulse by pulse and frequency fold back. the schematic of the current limitation circuitry for the pulse by pulse protection is shown in figure 7. the output power pdmos transistor is split in two parallel pdmos. the smallest one has a resistor in series, r sense . the current is sensed through rsense and if reaches the threshold, the mirror is unbalanced and the pdmos is switched off until the next falling edge of the internal clock pulse. due to this reduction of the on time, the output voltage decreases. since the minimum switch on time (necessary to avoid false overcurrent signal) is not enough to obtain a suf- ficiently low duty cycle at 250khz, the output current, in strong overcurrent or short circuit conditions, could in- crease again. for this reason the switching frequency is also reduced, so keeping the inductor current under its maximum threshold. the frequency shifter (see fig. 6) depends on the feedback voltage. as the feedback volt- age decreases (due to the reduced duty cycle), the switching frequency decreases too. frequency shifter clock generator ramp generator synchronizator clock ramp ibias_osc sync t d00in1131
5/19 AN1518 application note figure 7. current limitation circuitry error amplifier the voltage error amplifier is the core of the loop regulation. it is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235v), while the inverting input (fb) is con- nected to the external divider or directly to the output voltage. the output (comp) is connected to the external compensation network. the uncompensated error amplifier has the following characteristics: the error amplifier output is compared with the oscillator sawtooth to perform pwm control. pwm comparator and power stage this block compares the oscillator sawtooth and the error amplifier output signals generating the pwm signal for the driving stage. the power stage is a very critical block cause it has to guarantee a correct turn on and turn off of the pdmos. the turn on of the power element, or better, the rise time of the current at turn on, is a very critical parameter to compromise. at a first approach, it looks like the faster it is the rise time, the lower are the turn on losses. but there is a limit introduced by the recovery time of the recirculation diode. in fact when the current of the power element equals the inductor current, the diode turns off and the drain of the power is free to go high. but during its recovery time, the diode can be considered as an high value capacitor and this produces a very high peak current, responsible of many problems: n spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics. n turn on overcurrent causing a decrease of the efficiency and system reliability. n big emi problems. n shorter freewheeling diode life. the fall time of the current during the turn off is also critical. in fact it produces voltage spikes (due to the para- sitics elements of the board) that increase the voltage drop across the pdmos. transconductance 2300 m s low frequency gain 65db minimum sink/source voltage 1500 m a/300 m a output voltage swing 0.4v/3.65v input bias current 2.5 m a driver not a1 pwm vcc out a1/a2=95 i l rsense d00in1134 i off i i rth a2
AN1518 application note 6/19 in order to minimize all these problems, a new topology of driving circuit has been used and its block diagram is shown in fig. 8. the basic idea is to change the current levels used to turn on and off the power switch, according with the pd- mos status and with the gate clamp status. this circuitry allow to turn off and on quickly the power switch and to manage the above question related to the freewheeling diode recovery time problem. the gate clamp is necessary to avoid that vgs of the internal switch goes higher than vgsmax. the on/off control block avoids any cross conduction between the supply line and ground. figure 8. driving circuitry inhibit function the inhibit feature allows to put in stand-by mode the device. with inh pin higher than 2.2v the device is dis- abled and the power consumption is reduced to less than 100 m a. with inh pin lower than 0.8v, the device is enabled. if the inh pin is left floating, an internal pull up ensures that the voltage at the pin reaches the inhibit threshold and the device is disabled. the pin is also vcc compatible. thermal shutdown the shutdown block generates a signal that turns off the power stage if the temperature of the chip goes higher than a fixed internal threshold (150c). the sensing element of the chip is very close to the pdmos area, so ensuring an accurate and fast temperature detection. an hysteresis of approximately 20c avoids that the de- vices turns on and off continuously additional features and protections feedback disconnection in case of feedback disconnection, the duty cycle increases versus the maximum allowed value, bringing the output voltage close to the input supply. this condition could destroy the load. to avoid this dangerous condition, the device is turned off if the feedback pin remains floating. vgs max gate stop drive drain off on pdmos vout drain vcc i load c esr d00in1133 i off i on on/off control clamp l
7/19 AN1518 application note output overvoltage protection the overvoltage protection, ovp, is realized by using an internal comparator, which input is connected to the feedback, that turns off the power stage when the ovp threshold is reached. this threshold is typically 30% higher than the feedback voltage. when a voltage divider is requested for adjusting the output voltage (see figure 14), the ovp intervention will be set at: where r 1 is the resistor connected between the output voltage and the feedback pin, while r 2 is between the feedback pin and ground. zero load due to the fact that the internal power is a pdmos, no boostrap capacitor is required and so, the device works prop- erly also with no load at the output. in this condition it works in burst mode, with random repetition rate of the burst. closing the loop compensation network the output l-c filter of a step down converter contributes with 180 degrees phase shift in the control loop. for this reason a compensation network between the comp pin and ground is added. the simplest loop compen- sation network is shown in fig. 9. r c and c c introduce a pole and a zero in the open loop gain. c p doesnt affect really the system stability but is useful to reduce the noise of the comp pin. figure 9. compensation network the equivalent circuit of the error amplifier is shown in fig.10 figure 10. error amplifier equivalent circuit considering r c = 2.7k w , c c = 22nf and c p = 220pf (see fig. 14), the transfer function a o (s) of the error am- plifier and its compensation network becomes: where a vo = g m r o v ovp 1.3 r 1 r 2 + r 2 -------------------- v fb = e/a comp d00in1129a fb r c c c c p + - d v gm* d v d00in1130mod v+ r o 0.8m w c o 220pf a o s () a vo 1sr c c c + () s 2 r o c o c p + () r c c c sr o c c r o c o c p + () r c c c + + () 1 + + ------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------- - =
AN1518 application note 8/19 the poles and zeroes of this transfer function are: fp1 is the low frequency pole that sets the bandwidth while the zero fz1 is usually put near to the frequency of the double pole of the l-c filter (see below). fp2 is usually at a very high frequency. the transfer function of the l-c filter is given by: the poles and zeroes of this transfer function are: fo is the zero introduced by the esr of the output capacitor and it is very important to increase the phase margin of the control loop. f plc is the double pole of the l-c filter. the pwm gain is given by the following formula: where vosc max is the maximum value of a sawtooth waveform and vosc min is the minimum one. a voltage feed forward is realized to have g pwm constant. this feature is obtained generating a sawtooth waveform di- rectly proportional to the input voltage v cc . v oscmax - v oscmin = k v cc where k is equal to 0.076. therefore the pwm gain is also equal to this means that also if the input voltage changes, the error amplifier doesn't change its value to keep the loop in regulation, so ensuring a better line regulation and line transient response. to sumup the open loop gain can be written as: the gain and phase bode are plotted in figures 11 and 12. f p1 1 2 p r o c c --------------------------------- - 1 2 p 0.8 10 6 [] 22 10 9 C ---------------------------------------------------------------------- 9hz == = f p2 1 2 p r c c o c p + () ---------------------------------------------------- 1 2 p 2.7 10 3 220 10 12 C ------------------------------------------------------------------- - 134kh z == = f z1 1 2 p r c c c --------------------------------- - 1 2 p 2.7 10 3 22 10 9 C ------------------------------------------------------------- 2.673khz == = a lc s () 1 esr + c out s lc out s 2 esr s 1 + + ----------------------------------------------------------------------- = f plc 1 2 p lc out ------------------------------------------ - 1 2 p 22 10 6 C 100 10 6 C ---------------------------------------------------------------------- 3.393khz == = f o 1 2 p esr c out ------------------------------------------------ - 1 2 p 0.08 100 10 6 C ------------------------------------------------------ 19.89khz == = g pwm s () v cc v oscmax v oscmin C () --------------------------------------------------------------- = g pwm s () 1 k --- - const == gs () g pwm s () r 2 r 1 r 2 + -------------------- a o s () a lc s () =
9/19 AN1518 application note figure 11. module plot figure 12. phase plot the cut off frequency and the phase margin are: f c = 22.8khz phase margin = 35 0.1 1 10 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 10 0 10 20 30 40 50 60 70 80 90 frequenc y [hz] module (db) 0.1 1 10 100 1 . 10 3 1 . 10 4 1 . 10 5 1 . 10 6 200 160 120 80 40 0 frequenc y [hz] phase
AN1518 application note 10/19 application informations components selection input capacitor the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. the input capacitor has to absorb all this switching current that can be up to the load current divided by two (worst case, with duty cycle of 50%). for this reason, the quality of these capacitors has to be very high to minimize its power dissipation generated by the internal esr, so improving the system reliability and efficiency. the critical parameter is usually the rms current rating that has to be higher than the rms input current. the maximum rms input current (flowing through the input capacitor) is: where h is the expected system efficiency, d is the duty cycle and io the output dc current. this function reach- es its maximum value at d = 0.5 and the equivalent rms current is equal to i o divided by 2 (considering h = 1). the maximum and minimum duty cycles are: where v f is the freewheeling diode forward voltage and v sw the voltage drop across the internal pdmos. con- sidering the range d min to d max it is possible to determine the max i rms following through the input capacitor. different capacitors can be considered: - electrolytic capacitors. these are the most used cause are the cheapest ones and are available with a wide range of rms current ratings. the only drawback is that, considering a requested ripple current rating, they are physically larger than other capacitors. - ceramic capacitors. if available for the requested value and voltage rating, these capacitors have usually an higher rms current rating for a given physical dimension (due to the very low esr). the drawback is the quite high cost. - tantalum capacitor. very good tantalum capacitors are coming available, with very low esr and small size. the only problem is that they occasionally can burn if subjected to very high current during the charge. so, it is better avoid this type of capacitors for the input filter of the device. infact, they can be subjected to high surge current when connected to the power supply. output capacitor the output capacitor is very important to satisfy the output voltage ripple requirement. using a small inductor value is useful to reduce the size of the choke but increases the current ripple. so, to reduce the output voltage ripple a low esr capacitor is required. nevertheless, the esr of the output capacitor i rms i o d 2d 2 h -------------- - C d 2 h ------ - + = d max v out v f + v inmin v sw C ------------------------------------- and d min v out v f + v inmax v sw C --------------------------------------- ==
11/19 AN1518 application note introduces a zero in the open loop gain, that helps to increase the phase margin of the system. if the zero goes at very high frequency, its effect is negligible. for this reason, ceramic capacitors and very low esr capacitors in general should be avoided. tantalum and electrolytic capacitors are usually good for this use. below there is a list of some tantalum capacitors manufacturer. table 1. (*) poscap capacitors have characteristic very similar to tantalum ones. inductor the inductor value is very important cause it fixes the ripple current flowing through output capacitor. the ripple current is usually fixed at 20-40% of iomax, that is 0.4-0.8a with iomax = 2a. the inductor value is approximately obtained by the following formula: where t on is the on time of the internal switch, given by d t. for example, with v out = 3.3v, v in = 12v and d i o = 0.6a, the inductor value is about 17 m h. the peak current thought the inductor is given by: and it can be seen that if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. so, fixed the peak current, higher value of the inductor permit higher value for the output current. in the following table some inductor manufacturer are listed. table 2. manufacturer series cap value ( m f) rated voltage (v) esr (m w ) avx tps 100 to 470 4 to 35 50 to 200 kemet t494/5 100 to 470 4 to 20 30 to 200 sanyo poscap (*) tpa/b/c 100 to 470 4 to 16 40 to 80 sprague 595d 220 to 390 4 to 20 160 to 650 manufacturer series inductor value ( m h) saturation current (a) coilcraft do3316 15 to 33 2.0 to 3.0 coiltronics up1b 22 to 33 2.0 to 2.4 bi hm76-3 15 to 33 2.5 to 3.3 l v in v out C () i d ----------------------------------- t on = i pk i o i d 2 ---- - + =
AN1518 application note 12/19 layout considerations the layout of switching dc/dc converters is very important to minimize noise and interference. power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. high impedance paths (in particular the feedback connections) are susceptible to interference and so they should be as far as possible from the high current paths. below there is a layout example (fig. 13). the input and output loops are minimized to avoid radiation and high frequency resonance problems. the feedback pin connections to the external divider are very close to the device to avoid pick up noise. another important issue is the groundplane of the board. since the package has an exposed pad, it is very im- portant to connect it to an extended groundplane in order to reduce the thermal resistance junction to ambient. figure 13. layout example thermal considerations the dissipated power of the device is related to three different sources: - switch losses due to the not negligible r dson . these are equal to: where d is the duty cycle of the application. note that the duty cycle is theoretically given by the ratio between vout and vin, but in practical is quite higher than this value to compensate the losses of the overall application. due to this reason, the switch losses related to the r dson increases compared with the ideal case. l5973d cin d cout l inhibit si g nal to output volta g e vin vout gnd r1 r2 1 4 5 8 very small high current circulating path to minimize radiation and high frequency resonance problems output capacitor directly connected to heavy ground compensation network far from high current paths minimun size of feedback pin connections to avoid pickup connection to groundplane through vias extended groundplane on the bottom side p on r dson i out () 2 d =
13/19 AN1518 application note - switch losses due to its turn on and off. these are given by the following relation: where t on and t off are the overlap times of the voltage across the power switch and the current flowing into it during the turn on and turn off phases. t sw is the equivalent switching time. - quiescent current losses. where i q is the quiescent current. example: vin = 5v vout = 3.3v iout = 2a r dson has a typical value of 0.25 w @ 25c and increases up to a maximum value of 0.5 w @ 150c. we can consider a value of 0.4 w . t sw is approximately 70ns. i q has a typical value of 2.5ma @ v in = 12v. the overall losses are: the junction temperature of device will be: t j = t a + rth j-a p tot where t a is the ambient temperature and rth j-a is the thermal resistance junction to ambient. considering that the device in mounted on board with a good groundplane has a thermal resistance junction to ambient (rth j-a ) of about 42c/w and considering an ambient temperature of about 70c t j = 70 + 1.3 42 @ 125c p sw v in i out t on t off + () 2 ------------------------------------ - f sw v in i out t sw f sw == p q v in i q = p tot r dson i out () 2 dv in i out t sw f sw v in i q = + + = 0.4 2 2 0.7 5 2 70 10 9 C 250 10 3 52.510 3 C 13w , @ + + =
AN1518 application note 14/19 application circuit in figure 14 is shown the demo board application circuit, where the input supply voltage, vcc, can range from 4.4v to 25v due to the rated voltage of the input capacitor and the output voltage is adjustable from 1.235v to v cc . figure 14. demo board application circuit table 3. component list reference part number description manufacturer c1 10 m f, 25v tokin c2 10tpb100m 100 m f, 10v sanyo, poscap c3 c1206c221j5gac 220pf, 5%, 50v kemet c4 c1206c223k5rac 22nf, 10%, 50v kemet r1 5.6k, 1%, 0.25w neohm r2 3.3k, 1%, 0.25w neohm r3 2.7k, 1%, 0.25w neohm d1 stps2l25u 2a, 25v st l1 do3316p-153 15 m h, 3a coilcraft vinmax=25v c1 10uf 25v tokin d1 stps2l25u vcc comp gnd out fb inh sync vref l5973d 1 3 7 5 6 4 8 2 r3 4.7k l1 15uh coilcraft r1 5.6k r2 3.3k c3 22nf 3.3v c4 san y o poscap 100uf 10v vout=3.3v c2 220pf
15/19 AN1518 application note figure 15. pcb layout (component side) figure 16. pcb layout (bottom side) figure 17. pcb layout (front side) below some graphs show the tj versus output current in different conditions of the input and output voltage and some efficiency measurements. 42mm 34mm
AN1518 application note 16/19 figure 18. junction temperature vs. output current (v cc = 5v) figure 19. junction temperature vs. output current (v cc = 12v) figure 20. efficiency vs. output current (v cc = 5v) figure 21. efficiency vs. output curren (v cc = 12v)t 20 30 40 50 60 70 80 90 100 110 120 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 io(a) tj(c) vin=5v tamb=25c vo=2.5v vo=3.3v vo=1.8v 20 30 40 50 60 70 80 90 100 110 120 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 io (a) tj (c) vin=12v tamb=25c vo=3.3v vo=2.5v vo=5v 60 65 70 75 80 85 90 95 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 io (a) efficiency (%) vcc=5v vo=1.8v vo=2.5v vo=3.3v 60 65 70 75 80 85 90 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2. 4 io (a) efficiency (%) vcc=12v vo=2.5v vo=3.3v vo=5v
17/19 AN1518 application note application ideas positive buck-boost regulator the device can be used to realize an up-down converter with a positive output voltage. in figure is shown the schematic circuit of this topology for an output voltage of 12v. the input voltage can range from 5v and 35v. the output voltage is given by vo=vin d/(1-d), where d is duty cycle. the maximum output current is given by iout=1 (1-d). the current capability is reduced by the term (1-d) and so, for example, with a duty cycle of 0.5, and considering on average current following through the switch of 2a, the maximum output current deliverable to the load is 1a. this is due to the fact that the current flowing trough the internal power switch is delivered to the output only during the off phase. figure 22. positive buck-boost regulator buck-boost regulator in figure 23 is shown the schematic circuit to realize a standard buck-boost topology. the output voltage is given by vo=-vin d/(1-d). the maximum output current is equal to iout=1 (1-d), for the same reason of the up-down converter. an important thing to take in account is that the gnd pin of the device is connected to the negative output volt- age. so, the device undergoes a voltage equal to vin-vo, that has to be lower than 36v (maximum operating input voltage). figure 23. buck-boost regulator vin=5v c1 10uf 10v ceramic d1 stps2l25u vcc comp gnd out fb inh sync vref l5973d 1 3 7 5 6 4 8 2 r3 4.7k l1 15uh r1 5.6k r2 3.3k c3 22nf 3.3v c4 100uf 16v vout=12v/0.6a c2 220pf d2 stps2l25u m1 stn4ne03l vin=5v c1 10uf 10v ceramic d1 stps2l25u vcc comp gnd out fb inh sync vref l5973d 1 3 7 5 6 4 8 2 r3 4.7k l1 15uh r1 5.6k r2 3.3k c4 22nf 3.3v c5 100uf 16v vout=-12v/0.6a c3 220pf c2 10uf 25v ceramic
AN1518 application note 18/19 dual output voltage with auxiliary winding when two output voltages are required, it is possible to realize a dual output voltage converter by using a cou- pled inductor. during the on phase the current is delivered to vout while d2 is reverse biased. during the off phase the current is delivered, through the auxiliary winding, to the output voltage vout1. this is possible only if the magnetic core has stored a sufficient energy. so, to be sure that the application is working properly, the load related to the second output vout1 should be much lower than the load related to vout. figure 24. dual output voltage with auxiliary winding synchronization example two or more devices (up to 6) can be synchronized just connecting together the synchronization pin. in this case, the device with an slightly higher switching frequency value will work as master and the ones with a slightly lower switching frequency value will work as a slave. the device can also be synchronized from an external source. in this case the logic signal (see synchronization section) must have a frequency higher than the internal switching frequency of the device (250khz). figure 25. synchronization example vin=12v c1 10uf 25v ceramic d1 stps25l25u vcc comp gnd out fb inh sync vref l5973d 1 3 7 5 6 4 8 2 r3 4.7k c3 22nf 3.3v vout=3.3v 0.5a c2 220pf vout1=5v 50ma c5 47uf 10v lp=22uh d2 1n4148 c4 100uf 10v n1/n2=2 vcc gnd out fb inh sync vref 1 3 7 5 6 4 8 2 l5973d comp vcc gnd out fb inh sync vref 1 3 7 5 6 4 8 2 l5973d comp vin
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